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Memristor technology has become an attractive option for use in-memory architectures, in-memory computing, and logic applications. Memristor crossbar array performance is dependent upon sneak paths. Our research characterises the sneak paths in crossbar arrays where the current can sneak through non-selected cells. We present equations for characterising sneak paths as a function of the size of the array, resistance values, input voltage, and I/O switch-vector. We also derive formulas to calculate the number of sneak paths in various array sizes and describe conditions that determine the length of the sneak paths. The resulting equations enable us to predict the sneak paths and sneak path currents for various array sizes to determine the constraints to the resistive memristor circuit. Our work characterising sneak paths provides boundary conditions for applications that use memristor crossbar arrays and provides insight to memristor crossbar testing.

Sperm competition is widely recognized as a pervasive force of sexual selection. Theory predicts that across species increased risk of sperm competition should favor an increased expenditure on the ejaculate, a prediction for which there is much evidence. Sperm competition games have also been developed specifically for systems in which males adopt the alternative male mating tactics of sneaking copulations or guarding females. These models have not yet been tested in a comparative context, but predict that: across species male expenditure on the ejaculate should increase with increasing probability of a sneak mating; within species, sneaks should have the greater expenditure on the ejaculate; and the disparity in expenditure between sneaks and guards should be greatest in species with moderate risk of a sneak mating, and decline toward parity in species with low or high risk. Beetles in the genus Onthophagus are often characterized by dimorphic male morphologies that reflect the alternative mating tactics of sneak (minor males) and guard (major males). We conducted a comparative analysis across 16 species of male dimorphic onthophagines, finding that testes size increased across species with increasing frequency of the minor male phenotype. Minor males generally had the greater testes size, but across species the disparity between morphs was independent of the frequency of minor males. We present data on testes allometry from two populations of O. taurus that have undergone genetic divergence in the frequency of minor males. Consistent with the comparative analysis, these data support the notion that the relative frequency of sneaks in the population influences male expenditure on the ejaculate.

The automated sneak analysis software described in this paper works well on classic sneak examples. It correctly identifies sneak paths without falsely reporting on nonexistent sneaks. It has been tried out on much larger real-world examples, and reproduces the kind of behavior that it had demonstrated on the classic sneaks. Future development of the tool will enable the exploration of internal states of complex components such as ECUs. In addition of provision to complete a sneak analysis in the presence of failures will further enhance the tool. The use of simulation and identification of significant system operation has enabled this level of performance. The system is able to use qualitative simulation early in the design process, to identify potential sneaks as early as possible. It can use the industry-standard simulator Saber later in the design process, to give a more detailed analysis. In each case, component models are not specific to sneak circuit analysis, but can be used to verify the operation of the design, to generate a failure modes and effects analysis (FMEA) report, and to provide information useful for building diagnostic systems.

It is found in the latest research works that there are sneak circuit phenomena in power converters, which would normally be ignored but finally cause various problems. Therefore, it is necessary to find out and analyze sneak circuits. Under certain conditions, sneak circuit phenomena caused by parasitic parameters are first found in a Boost converter operating at discontinuous conduction mode (DCM). A detailed investigation into the impacts of sneak circuits on the operation performances of the DCM Boost converter is achieved. It is found that the operation performances of the DCM Boost converter will be adversely affected when the sneak circuits appear. Then, the conditions of the sneak circuits are derived. Furthermore, design guidelines for reducing or eliminating the sneak circuit phenomena are presented. Finally, the theoretical analyses are demonstrated with both simulation and experimental results.

In a memristor crossbar array, functioning as a memory array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this paper, we study the sneak path problem in crossbar arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are modeling the error channel induced by sneak paths, a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method, we match a constraint on the array content that guarantees sneak-path free readout, determine the resulting capacity, and provide an efficient encoder that achieves the capacity.

Since the emergence of memristors (or memristive devices), how to integrate them into arrays has been widely investigated. After years of research, memristor crossbar arrays have been proposed and realized with potential applications in nonvolatile memory, logic and neuromorphic computing systems. Despite the promising prospects of memristor crossbar arrays, one of the main obstacles for their development is the so-called sneak-path current causing cross-talk interference between adjacent memory cells and thus may result in misinterpretation which greatly influences the operation of memristor crossbar arrays. Solving the sneak-path current issue, the power consumption of the array will immensely decrease, and the reliability and stability will simultaneously increase. In order to suppress the sneak-path current, various solutions have been provided. So far, some reviews have considered some of these solutions and established a sophisticated classification, including 1D1M, 1T1M, 1S1M (D: diode, M: memristor, T: transistor, S: selector), self-selective and self-rectifying memristors. Recently, a mass of studies have been additionally reported. This review thus attempts to provide a survey on these new findings, by highlighting the latest research progress realized for relieving the sneak-path issue. Here, we first present the concept of the sneak-path current issue and solutions proposed to solve it. Consequently, we select some typical and promising devices, and present their structures and properties in detail. Then, the latest research activities focusing on single-device structures are introduced taking into account the mechanisms underlying these devices. Finally, we summarize the properties and perspectives of these solutions.

Emerging nonvolatile memory (NVM) technologies, such as resistive random access memories (RRAM) and phase-change memories (PCM), are an attractive option for future memory architectures due to their nonvolatility, high density, and low-power operation. Not withstanding these advantages, they are prone to high defect densities due to the nondeterministic nature of the nanoscale fabrication. We examine the fault models and propose an efficient testing technique to test crossbar-based NVMs. The typical approach to testing memories entails testing one memory element at a time. This is time consuming and does not scale for the dense, RRAM or PCM-based memories. We propose a testing scheme based on “sneak-path sensing” to efficiently detect faults in the memory. The testing scheme uses sneak paths inherent in crossbar memories, to test multiple memory elements at the same time, thereby reducing testing time. We designed the design-for-test support necessary to control the number of sneak paths that are concurrently enabled; this helps control the power consumed during test. The proposed scheme enables and leverages sneak paths during test mode, while still maintaining a sneak path free crossbar during normal operation.

In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method we match a constraint on the array content that guarantees sneak-path free readout, and calculate the resulting capacity.

The rise of data-intensive computational loads has exposed the processor-memory bottleneck in Von Neumann architectures and has reinforced the need for in-memory computing using devices such as memristors. Existing literature on computing Boolean formula using sneak-paths in nanoscale memristor crossbars has only focussed on short Boolean formula. There are two open questions: (i) Can one synthesize sneak-path based crossbars for computing large Boolean formula? (ii) What is the size of a memristor crossbar that can compute a given Boolean formula using sneak paths? In this paper, we make progress on both these problems. First, we show that the number of rows and columns required to compute a Boolean formula is at most linear in the size of the Reduced Ordered Binary Decision Diagram representing the Boolean function. Second, we demonstrate how Boolean Decision Diagrams can be used to synthesize nanoscale crossbars that can compute a given Boolean formula using naturally occurring sneak paths. In particular, we synthesize large logical circuits such as 128-bit adders for the first-time using sneak-path based crossbar computing.

Attempts by males to steal fertilizations from other males are common in many species. In some sticklebacks, males also are known to steal eggs from the nests of rivals and to carry them back to their own nests. However the genetic consequences of these nest-raiding behaviors seldom have been investigated. Here we assess genetically the prevalence of sneaked fertilizations and egg stealing, and we describe the mating system in a natural population of the fifteenspine stickleback. Six microsatellite markers were developed and employed to assay a total of 1307 embryos from 28 nests. Guardian males and all nest-holding males in the local area also were genotyped for two to six loci Analysis of male genotypes and those of embryos revealed that five of the 28 nests (18%) contained progeny from sneaked fertilizations, and that four of the 24 nests (17%) with resident males contained stolen egg clutches Comparisons of the composite DNA genotypes of nest-holding males against those of inferred sneakers implicated one nest holder as the sneaker of a nest seven meters from his own. Also, the genetic data demonstrated that nests of males frequently contain eggs from multiple females. The multilocus genotypes of inferred mothers indicated that females mate with multiple males, sometimes over distances greater than one kilometer.

An overview of the development and application of a systems analysis technique will be presented in this paper. The technique is based on an aerospace discovery that topological criteria exist that can be used to recognize unplanned operational modes of a system. Software sneak analysis is based on successful electrical sneak circuit analysis techniques which have been applied to over 70 commercial, military, nuclear, and space systems. The similarities of electrical current and software logic flow implied the possibility of an analogous technique for software analysis. The technique involves encoding software data for computer processing. The computer processing produces simplified, topological network trees which represent the software system. The network trees are analyzed by the application of sneak clues to identify and report all sneak conditions. There have been seven successful applications of software sneak analysis to computer systems involving over twelve different computer languages. The results obtained from a variety of complex electrical and software systems analyses will also be presented as positive collaboration for this analysis technique.

The sneak path current (SPC) is the inevitable issue in crossbar memory array while implementing high-density storage configuration. The crosstalks are attracting much attention, and the read accuracy in the crossbar architecture is deteriorated by the SPC. In this work, the sneak path current problem is observed and investigated by the electrical experimental measurements in the crossbar array structure with the half-read scheme. The read margin of the selected cell is improved by the bilayer stacked structure, and the sneak path current is reduced ~20% in the bilayer structure. The voltage-read stress-induced read margin degradation has also been investigated, and less voltage stress degradation is showed in bilayer structure due to the intrinsic nonlinearity. The oxide-based bilayer stacked resistive random access memory (RRAM) is presented to offer immunity toward sneak path currents in high-density memory integrations when implementing the future high-density storage and in-memory computing applications.

This paper describes a novel readout scheme that enables the complete cancellation of sneak currents in resistive switching random-access memory (RRAM) crossbar array. The current-mode readout is employed in the proposed readout, and a few critical advantages of the current-mode readout for crossbar RRAM are elucidated in this paper. The proposed scheme is based on a floating readout scheme for low power consumption, and one more sensing port is introduced using an additional reference word line. From the additional port, information on the sneak current amount is collected, and simple current-mode arithmetic operations are implemented to cancel out the sneak current from the sensing current. In addition, a simple method of handling the overestimated-sneak-current issue is described. The proposed scheme is verified using HSPICE simulation. Moreover, an example of a current-mode sense amplifier realizing the proposed cancelling technique is presented. The proposed sense amplifier can be implemented with less hardware overhead compared to the previous works.

Beginning in late 1967, The Boeing Company in Houston, Tex., developed a computer-aided electrical-systems-analysis technique to help assure troublefree operation of NASA's Apollo and Skylab hardware. The technique, called sneak- circuit analysis,'' is based on the discovery that there are topological criteria that enable prerecognition of a circuit to exhibit unplanned modes of operation. The results of sneak-circuit analygis over the last 5 years have shown that it is no longer necessary to accept the supposition that a few operational surprises are inevitable in complex electrical systems. Electrical systems can be made foolproof from the operational point of view; specifically, sneakcircuit analysis will disclose all latent current paths, inadvertent inhibits or activations, ambiguous system indications, and misleading console labels. Relay races, sneak grounds, and powersupply crossties are included. This article presents an overview of these problems and other products of the analysis as found in aerospace, commercial, and nuclear systems. (auth)

A cold-gas test campaign was conducted on a subscale dual-bell nozzle operating under sea-level conditions to study the unsteady flow conditions encountered during sneak transition, which is a phenomenon prevalent just before final transition occurs. The study reveals that the flow during sneak transition is highly unsteady and is the major source of side-load generation in the dual-bell nozzle preceding the final transition. Statistical analysis suggests that, as the separation front moves into the region of wall inflection, the separated shear layer gradually comes in close proximity to the nozzle extension wall that alters the flow development process in the recirculation/backflow region considerably. This sets the entire backflow region into pressure fluctuations, making the flow conditions highly unsteady. It is further observed that the flow during sneak transition is associated with low frequencies in the vicinity of the separation location (0.8 kHz), which decreases as the sneak transition nozzle pressure ratio is approached (0.2 kHz).

In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings. The new method requires fewer reading steps compared to previously reported techniques, and has a very small impact on the memory density. To verify the underlying theory, the proposed system is simulated using Synopsys HSPICE showing the ability to achieve a 100% sneak-path error-free memory. In addition, the effect of quantization bits on the system performance is studied.

Several memory vendors are pursuing different kinds of memory cells that can offer high density, non-volatility, high performance, and high endurance. There are several on-going efforts to architect main memory systems with these new NVMs that can compete with traditional DRAM systems. Each NVM has peculiarities that require new microarchitectures and protocols for memory access. In this work, we focus on memristor technology and the sneak currents inherent in memristor crossbar arrays. A read in state-of-the-art designs requires two consecutive reads; the first measures background sneak currents that can be factored out of the current measurement in the second read. This paper introduces a mechanism to reuse the background sneak current measurement for subsequent reads from the same column, thus introducing "open-column" semantics for memristor array access. We also examine a number of data mapping policies that allow the system to balance parallelism and locality. We conclude that on average, it is better to prioritize locality; our best design yields a 20% improvement in read latency and a 26% memory power reduction, relative to the state-of-the-art memristor baseline.

Resistive memory is a promising technology for achieving unprecedented storage densities and new in-memory computing features. However, to fulfill their promise, resistive memories require array architectures suffering from a severe interference effect called “sneak paths.” In this paper, we address the sneak-path problem through a communication-theory framework. Starting from the fundamental problem of readout with parallel-resistance interference, we develop several tools for detection and coding that significantly improve memory reliability. For the detection problem, we formulate and derive the optimal detector for a realistic array model, and then propose simplifications that enjoy similarly good performance and simpler implementation. Complementing detection for better error rates is done by a new coding scheme that shapes the stored bits to get lower sneak-path incidence. For the same storage rates, the new coding scheme exhibits error rates lower by an order of magnitude compared to known shaping techniques.

Sneak circuit analysis (SCA) is a functional reliability analysis technique with the potential of detecting unintended and thereby undesirable system operation. SCA can prevent unintended operational characteristics in a system when performed during the design phase of project development. Costs of correcting undetected system function continue to escalate through development to the deployment of a fully operational system. Detection of sneak conditions with SCA can prevent costly redesign and testing during the qualification and production phase of a project. The automation of the SCA process with the use of existing computer resources and proven sneak circuit detection techniques is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>