This article introduces a quantized chip-firing model with close connections to the theory of rational lattice paths and rational parking functions. Given a graph with a sink and positive integers a,b,c with gcd(a,b)=1, a set S of vertices fires by the following rule. Each vertex in S provisionally sends c chips to the sink and a/b chips to each non-sink neighbor outside of S. The novel feature is that the total number of chips leaving from or arriving at any vertex gets rounded down to the nearest integer before being finalized. We define the notions of chip configurations being superstable, k-stable, or k-skeletal in this model. When c=1 and the graph is complete, superstable configurations correspond to rational parking functions. There is a bijection between superstable configurations and k-skeletal configurations for each k. We establish these results by building a combinatorial theory of k-skeletal rational lattice paths (both unlabeled and labeled) and translating that theory to chip configurations. There is a group structure on the set of chip configurations modulo firing and borrowing moves. We show that this group is isomorphic to the product of b-1 copies of the integers
Chip-firing is a combinatorial game played on a graph, in which chips are placed and dispersed on the vertices until a stable configuration is achieved. We study a chip-firing variant on an infinite, rooted directed $k$-ary tree, where we place $k^n$ chips labeled $1,2,3,\dots, k^n$ on the root for some nonnegative integer $n$. A vertex $v$ can fire if it has at least $k$ chips; when it fires, $k$ chips are selected, and the chip with the $i$th smallest label is sent to the $i$th leftmost child of $v$. A stable configuration is reached when no vertices can fire. In this paper, we prove numerous properties of the stable configuration, such as that chips land on vertices in ranges and the lengths of those ranges. We also describe where each chip can land. This helps us describe possible stable configurations of the game.
Quantum Electronic Design Automation (Q-EDA) is emerging as quantum chips move from laboratory prototypes to scalable engineering systems. This paper argues that superconducting quantum chip design is approaching a "SPICE moment" similar to early classical EDA, where growing qubit scale, control complexity, frequency planning, packaging, process variation, and cryogenic measurement feedback require a shift from experience-based design to model-driven engineering. We propose a Quantum Chip Paradigm Framework that treats Q-EDA not only as software, but as part of the quantum chip development paradigm. Unlike classical HDL-first design, quantum chip design must begin with physical structures such as Josephson junctions, resonators, couplers, readout elements, control lines, and packaging environments. The framework emphasizes PCell-based modeling, SPICE-Q simulation, Quantum PDKs, and design-technology-measurement co-optimization. We further outline a hierarchical Q-EDA system spanning physical structures, qubit PCells, logical qubits, quantum arithmetic, functional quantum IP, and Quantum SoC systems. The key goal is to turn physical models, layout rules, simulation results, fabricat
The increasing complexity of modern very-large-scale integration (VLSI) design highlights the significance of Electronic Design Automation (EDA) technologies. Chip placement is a critical step in the EDA workflow, which positions chip modules on the canvas with the goal of optimizing performance, power, and area (PPA) metrics of final chip designs. Recent advances have demonstrated the great potential of AI-based algorithms in enhancing chip placement. However, due to the lengthy workflow of chip design, the evaluations of these algorithms often focus on intermediate surrogate metrics, which are easy to compute but frequently reveal a substantial misalignment with the end-to-end performance (i.e., the final design PPA). To address this challenge, we introduce ChiPBench, which can effectively facilitate research in chip placement within the AI community. ChiPBench is a comprehensive benchmark specifically designed to evaluate the effectiveness of existing AI-based chip placement algorithms in improving final design PPA metrics. Specifically, we have gathered 20 circuits from various domains (e.g., CPU, GPU, and microcontrollers). These designs are compiled by executing the workflow
Chip-firing is a combinatorial game played on a graph in which we place and disperse chips on vertices until a stable state is reached. We study a chip-firing variant played on an infinite rooted directed $k$-ary tree, where we place $k^\ell$ chips on the root for some positive integer $\ell$, and we say a vertex $v$ can fire if it has at least $k$ chips. A vertex fires by dispersing one chip to each out-neighbor. Once every vertex has less than $k$ chips, we reach a stable configuration since no vertex can fire. We determine the exact number and properties of the possible stable configurations of chips in the setting where chips are distinguishable.
A free-space-to-chip pipeline is proposed to efficiently transport single atoms from a magneto-optical trap to an on-chip evanescent field trap. Due to the reflection of the dipole laser on the chip surface, the conventional conveyor belt approach can only transport atoms close to the chip surface but with a distance of about one wavelength, which prevents efficient interaction between the atom and the on-chip waveguide devices. Here, based on a two-layer photonic chip architecture, a diffraction beam of the integrated grating with an incident angle of the Brewster angle is utilized to realize free-space-to-chip atom pipeline. Numerical simulation verified that the reflection of the dipole laser is suppressed and that the atoms can be brought to the chip surface with a distance of only 100nm. Therefore, the pipeline allows a smooth transport of atoms from free space to the evanescent field trap of waveguides and promises a reliable atom source for a hybrid photonic-atom chip.
Quantum repeaters are employed in quantum communication to overcome the long-distance transmission loss of quantum states. The quantum repeater is based on various key technologies, including quantum entanglement swapping, quantum memory, and entanglement purification. In particular, quantum purification can distil high-quality entanglement from the degraded entangled states which is propagating through noisy quantum communication channels. Although previous reports have demonstrated on-chip entanglement swapping and teleportation through the less-noisy channel, current entanglement purification experiments still rely on off-chip discrete devices, leading to limitations on scalability, stability, and controllability. In this paper, for the first time, we demonstrated chip-to-chip hyperentanglement distribution and quantum entanglement purification based on integrated silicon chips. Path-encoded high-dimensional entangled photon pairs are produced on the chip, converted to fibre-based polarization-spatial hyperentanglement by grating couplers, distributed to the receiver silicon chip, and finally purified by consuming the spatial degree of freedom. Our purification scheme by integra
In this article, we provide three formulas allowing to compute the minimum amount of initial chips leading to an infinite Chip-firing game, answering a question originally posed by Björner and Lovász in 1992. These formulas hold for strongly connected directed loop-free multigraphs and generalize what was already known in the Eulerian case. The various proofs heavily rely on a notion of dynamical bound, which allows to encode some specific sequences of chip configurations.
We investigate a variant of the chip-firing process on the infinite path graph: rather than treating the chips as indistinguishable, we label them with positive integers. To fire an unstable vertex, i.e. a vertex with more than one chip, we choose any two chips at that vertex and move the lesser-labeled chip to the left and the greater-labeled chip to the right. This labeled version of the chip-firing process exhibits a remarkable confluence property, similar to but subtler than the confluence that prevails for unlabeled chip-firing: when all chips start at the origin and the number of chips is even, the chips always end up in sorted order. Our proof of sorting relies upon an independently interesting lemma concerning unlabeled chip- firing which says that stabilization preserves a natural partial order on configurations. We also discuss some extensions of this sorting phenomenon to other graphs (variants of the infinite path), to other initial configurations, and to other Cartan-Killing types.
Transmitting entangled states over long distances is crucial for developing quantum networks. Previous demonstrations using satellites or fibers relied on photon pairs generated from bulk crystal arrangements. Polarization entanglement distribution based on CMOS-compatible silicon chips has long been restricted to lab-scale demonstrations spanning only a few meters, due to the difficulty of achieving sufficient off-chip brightness. We report a silicon chip platform that provides an off-chip entangled photon pair brightness ranging from 8,000 to 460,000 pairs per second, exceeding previous reports by three orders of magnitude. The entanglement fidelity reaches 99.85(6)% and 97.90(3)%, respectively. After addressing key challenges in long distance entanglement distribution over deployed fiber, including phase drift and chromatic dispersion, entangled photons were successfully distributed over 155 km (66 dB loss). These results demonstrate that CMOS-compatible silicon chips can perform competitively with bulk crystal sources and represent an important step toward scalable, chip-based quantum networks.
Recent progress in humanoid robots has unlocked agile locomotion skills, including backflipping, running, and crawling. Yet it remains challenging for a humanoid robot to perform forceful manipulation tasks such as moving objects, wiping, and pushing a cart. We propose adaptive Compliance Humanoid control through hIsight Perturbation (CHIP), a plug-and-play module that enables controllable end-effector stiffness while preserving agile tracking of dynamic reference motions. CHIP is easy to implement and requires neither data augmentation nor additional reward tuning. We show that a generalist motion-tracking controller trained with CHIP can perform a diverse set of forceful manipulation tasks that require different end-effector compliance, such as multi-robot collaboration, wiping, box delivery, and door opening.
An atom chip has been fabricated for the study of interactions between $^{87}$Rb Rydberg atoms and a Au surface. The chip tightly confines cold atoms by generating high magnetic field gradients using microfabricated current-carrying wires. These trapped atoms may be excited to Rydberg states at well-defined atom-surface distances. For the purpose of Rydberg atom-surface interaction studies, the chip has a thermally evaporated Au surface layer, separated from the underlying trapping wires by a planarizing polyimide dielectric. Special attention was paid to the edge roughness of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface.
Chip Guard is a new approach to symbol-correcting error correction codes. It can be scaled to various data burst sizes and reliability levels. A specific version for DDR5 is described. It uses the usual DDR5 configuration of 8 data chips, plus 2 chips for ECC and metadata, with 64-bit bursts per chip, to support whole-chip correction reliably and with high probity (reporting of uncorrectable faults). Various numbers of metadata bits may be supported with defined tradeoffs for reliability and probity. The method should correct all bounded faults of a single chip, with less than 1 in 10^12 chance of failing to correct unbounded faults in one chip, or less than 1 in 10^12 chance of failure to detect an uncorrected fault which affects multiple chips.
Quantum teleportation is a crucial function in quantum networks. The implementation of photonic quantum teleportation could be highly simplified by quantum photonic circuits. To extend chip-to-chip teleportation distance, more effort is needed on both chip design and system implementation. In this work, we demonstrate a chip-to-chip photonic quantum teleportation over optical fibers under the scenario of star-topology quantum network. Time-bin encoded quantum states are used to achieve a long teleportation distance. Three photonic quantum circuits are designed and fabricated on a single chip, each serving specific functions: heralded single-photon generation at the user node, entangled photon pair generation and Bell state measurement at the relay node, and projective measurement of the teleported photons at the central node. The unbalanced Mach-Zehnder interferometers (UMZI) for time-bin encoding in these quantum photonic circuits are optimized to reduce insertion losses and suppress noise photons generated on the chip. Besides, an active feedback system is employed to suppress the impact of fiber length fluctuation between the circuits, achieving a stable quantum interference for
A lattice beam configuration which results in an isotropic 3D trap near the surface of an atom chip is described. The lattice is formed near the surface of a reflectively coated atom chip, where three incident beams and three reflected beams intersect. The coherent interference of these six beams form a phase-stable optical lattice which extends to the surface of the atom chip. The lattice is experimentally realized and the trap frequency is measured. Degenerate Raman sideband cooling is performed in the optical lattice, cooling 80 million atoms to 1.1 $μ$K.
In this article, we proposed a programmable 16-channel photonic solver for quadratic unconstrained binary optimization (QUBO) problems. The solver is based on a hybrid optoelectronic scheme including a photonic chip and the corresponding electronic driving circuit. The photonic chip is fabricated on silicon on insulator (SOI) substrate and integrates high-speed electro-optic modulators, thermo-optic phase shifters and photodetectors to conduct the 16-dimensional optical vector-matrix multiplication (OVMM). Due to the parallel and low latency propagation of lightwave, the calculation of the QUBO cost function can be accelerated. Besides, the electronic processor is employed to run the heuristic algorithm to search the optimal solution. In the experiment, two 16-dimensional randomly generated QUBO problems are solved with high successful probabilities. To our knowledge, it is the largest scale of programmable and on-chip photonic solver ever reported. Moreover, the computing speed of the OVMM on photonic chip is ~2 TFLOP/s. It shows the potential of fast solving such optimization problems with integrated photonic systems.
Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm$^2$ and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of $αT^{-3}$, with $α= 7.7-15.4$ K$^4$$μ$m$^2$/nW. The $T^{-3}$ relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various hea
In this paper, we explore the notion of a \emph{self-reachable} chip configuration on a simple graph, that is a chip configuration which can be re-obtained from itself after a (nonempty) sequence of vertex firings. In particular, we focus on the case of trees and provide a characterization for such configurations, as well as show that all self-reachable configurations with the same number of chips on a tree are reachable from one another. We conclude with a recursive enumeration formula for the number of self-reachable configurations.
Spiking Neural Networks (SNNs) are gaining increasing attention for their biological plausibility and potential for improved computational efficiency. To match the high spatial-temporal dynamics in SNNs, neuromorphic chips are highly desired to execute SNNs in hardware-based neuron and synapse circuits directly. This paper presents a large-scale neuromorphic chip named Darwin3 with a novel instruction set architecture(ISA), which comprises 10 primary instructions and a few extended instructions. It supports flexible neuron model programming and local learning rule designs. The Darwin3 chip architecture is designed in a mesh of computing nodes with an innovative routing algorithm. We used a compression mechanism to represent synaptic connections, significantly reducing memory usage. The Darwin3 chip supports up to 2.35 million neurons, making it the largest of its kind in neuron scale. The experimental results showed that code density was improved up to 28.3x in Darwin3, and neuron core fan-in and fan-out were improved up to 4096x and 3072x by connection compression compared to the physical memory depth. Our Darwin3 chip also provided memory saving between 6.8X and 200.8X when mappi
Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.